The present invention generally relates to memory devices, and more particularly, to tracking memory paths in memory devices.
Referring to FIG. 1, a circuit diagram of a conventional memory device 100 is shown. The memory device 100 includes an internal clock line 102, a plurality of memory arrays including first and second memory arrays 104a and 104b, a first pre-charge transistor 106, a first transmission gate 108, a row address decoder (XDEC) 110, a reference column 112, a sense signal generator 114, a reset clock line 116, a sense amplifier 118, and a pre-charge line 120. A clock generator (not shown) generates internal clock signals in the memory device 100 that traverse along the internal clock line 102. The first and second memory arrays 104a and 104b include a plurality of bit line columns 122, one of which is shown. The bit line column 122 includes a plurality of bit lines 124, one of which is shown. The bit line 124 is connected to a plurality of bit cells (or memory cells) that are further connected to a plurality of word lines (not shown). The reference column 112 includes a reference bit line (RBL) 126. The sense signal generator 114 includes a second pre-charge transistor 128 and a second transmission gate 130.
The bit line 124 and the RBL 126 are pre-charged to a first predefined threshold voltage by a pre-charge signal (PRCH) generated by the pre-charge line 120 before a read operation. Pre-charging of the bit line 124 and the RBL 126 results in a high read current and a fast read operation. The first predefined threshold voltage depends on the voltage (VDD) applied to the memory device 100 and usually about 90 to 98 percent of the applied voltage VDD. The bit line 124 and the RBL 126 are pre-charged by the first and second pre-charge transistors 106 and 128, respectively. Drain terminals of both the pre-charge transistors 106 and 128 are connected to the voltage (VDD) line. The internal clock signal is provided to the XDEC 110 to start the read operation, which generates a word line enable right (WLR) signal 132a and a word line enable left (WLL) signal 132b, to enable one or more of the plurality of word lines.
The clock generator further generates a sense clock signal that initiates discharging of the RBL 126 on reaching the reference column 112. The reference column 112 includes reference bit cells that are connected to the RBL 126 and track the bit line 124 by way of the sense clock signal in the reference column 112. The bit line 124 and the RBL 126 discharge to a second predefined threshold voltage to create a required potential difference (ΔV) on the bit line 124, and he first transmission gate 108 selects the bit line 124, and the second transmission gate 130 selects the RBL 126. The second predefined threshold voltage is the voltage at which the sense amplifier 118 needs to be activated to generate an output of the read operation on sensing ΔV.
Thereafter, the sense signal generator 114 generates a reset clock signal on the reset clock line 116, and a sense amplifier enable right (SAER) signal 134a and a sense amplifier enable left (SAEL) signal 134b when the RBL 126 discharges to the second pre-defined threshold voltage. The SAER and SAEL signals 134a and 134b enable the sense amplifier 118 to read the data stored on the bit line 124. The output of the bit line 124 is denoted by Q.
The memory device 100 includes two functional paths that are activated at the beginning of a memory read operation. The first functional path performs the actual memory operation and is the path traversed by the internal clock signal to the XDEC 110, paths traversed by the WLR and WLL signals 132a and 132b, the enabled word line, and the bit line 124 and is referred to as ‘memory operation path’. The second path enables the sense amplifier 118 using the SAER and SAEL signals 134a and 134b, resets the memory device 100 and is the path traversed by the sense clock signal to the reference column 112, and that traversed by the SAER and SAEL signals 134a and 134b to the sense amplifier 118. The second path is referred to as ‘self-time path’. For proper and accurate execution of read/write operations and resetting of the memory after the operation, it is important that the self-time path accurately tracks the memory operation path.
FIG. 2 shows a schematic block diagram of a conventional memory device 200, in which a self-time path is shown. The memory device 200 includes a local control circuit 202, a row address decoder (XDEC) 204, a reference column 206, a memory array 208, a sense amplifier 210 and a sense line 212. The local control circuit 202 includes a clock generator 214 for generating internal clock and sense clock signals, and a sense signal generator 216 for generating sense enable and write completion signals for read and write operations respectively. The reference column 206 includes a read reference bit line (read RBL) 218 and a write reference bit line (write RBL) 220. The memory array 208 includes a plurality of bit line columns 222, one of which is shown, and the bit line column 222 includes a plurality of bit lines 224, one of which is shown. The bit line 224 is connected to a plurality of bit cells that are further connected to a plurality of word lines 226, one of which is shown.
The memory read/write operation starts with the clock generator 214 simultaneously generating the internal and sense clock signals on receiving a memory clock signal. In the memory operation path, the internal clock signal reaches the XDEC 204 in time T1, a word line enable signal generated by the XDEC 204 enables the word line 226 and initiates discharging of the bit line 224 in time T2, and the bit line 224 discharges in time T3. Therefore, the total time required for the completion of the memory read/write operation is T1+T2+T3. In the self-time path, the sense clock signal reaches the reference column 206 and initiates discharging of the read RBL 218 or the write RBL 220, based on whether a memory read or write operation are being performed. The sense enable signal/write completion signal is generated by the sense signal generator 216 once the read RBL 218 is discharged to ΔV or the write RBL 220 is discharged to the defined write margin. The sense enable signal traverses the sense line 212 to enable the sense amplifier 210 and the sense enable/write completion signal resets the memory device 200 for the next operation. The circuit associated with the self-time path is referred to as a ‘self-time circuit’ and includes the self-time path, the reference column 206, the sense signal generator 216, and the sense line 212.
Reference bit cells are connected to the read RBL 218/write RBL 220 to track the bit line 224. In other words, the time T3 required for discharging the bit line 224 is tracked by discharging the read RBL 218/write RBL 220. However, the tracking is not accurate since resistances of the bit line 224 and read RBL 218/write RBL 220 do not match. Further, the time T2 required to enable the bit line 224 after generation of the word line enable signal cannot be tracked accurately by the sense enable signal because of the mismatch in the resistances and capacitances (RC) of the word line 226 and the sense line 212. Moreover, the self-time path does not track time T1. Therefore, the self-time path takes time equal to roughly T2+T3 as opposed to time T1+T2+T3 taken by the memory operation path.
Different memory devices operate in different configurations and generate different aspect ratios based on the bit cell being selected from the memory array 208 for a memory operation. The mismatch between the memory path and the self-time path changes with a change in the aspect ratios. For example, the time mismatch because of T2 is maximum at far ends and minimum at near ends of the word line 226 and the sense line 212 and results in a considerable difference in the ΔV/write margin values at the far and near ends. In addition, voltage and temperature changes affect the RC delays of the word line 226 and sense line 212 differently, contributing to further time mismatch between the two paths.
The time mismatch between the memory operation and self-time paths introduces inconsistencies in ΔV or write margins and lowers the performance of the memory device 200 in terms of output accuracy, timing, and power consumption. For example, activating the sense amplifier 210 when ΔV is less than the required voltage may result in a failure of the read operation. Further, activating the sense amplifier 210 when ΔV is more than the required voltage increases the memory access time and power consumption of the sense amplifier 210. Similarly, slow write completion may increase the write operation time and power consumption or result in a failure of the write operation because of violation of the write cycle time, whereas faster write completion may result in a failure of the write operation. Thus, the self-time circuit in the memory device 200 does not track the memory operation accurately and does not account for variations in the timing mismatch that occurs due to different aspect ratios, varying voltages and temperature effects on the timing critical paths, and process variations on the bit cells and the sense amplifier 210.
Therefore, there is a need for a memory device with a self-time circuit that accurately tracks memory read/write operations, that adapts to different aspect ratios and process variations of the memory device, that achieves a fast reset of the memory device, and that overcome the above-mentioned limitations of existing memory devices.